ARM Cortex-X1

The Cortex-X1 design is based on the ARM Cortex-A78, but redesigned for purely performance instead of a balance of performance, power, and area (PPA).^[1]

The Cortex-X1 is a 5-wide decode out-of-order superscalar design with a 3K macro-OP (MOPs) cache. It can fetch 5 instructions and 8 MOPs per cycle, and rename and dispatch 8 MOPs, and 16 μOPs per cycle. The out-of-order window size has been increased to 224 entries. The backend has 15 execution ports with a pipeline depth of 13 stages and the execution latencies consists of 10 stages. It also features 4x128b SIMD units.^[3][4][5][6]

ARM claims the Cortex-X1 offers 30% faster integer and 100% faster machine learning performance than the ARM Cortex-A77.^[3][4][5][6]

The Cortex-X1 supports ARM's DynamIQ technology, expected to be used as high-performance cores when used in combination with the ARM Cortex-A78 mid and ARM Cortex-A55 little cores.^[1][2]

• Around 20% performance improvement (+30% from A77)^[7]
  • 30% faster integer
  • 100% faster machine learning performance
• Out-of-order window size has been increased to 224 entries (from 160 entries)
• Up to 4x128b SIMD units (from 2x128b)
• 15% more silicon area
• 5-way decode (from 4-way)
• 8 MOPs/cycle decoded cache bandwidth (from 6 MOPs/cycle)
• 64 KB L1D + 64 KB L1I (from 32/64 KB L1)
• Up to 1 MB/core L2 cache (from 512 KB/core max)
• Up to 8 MB L3 cache (from 4 MB max)

The Cortex-X1 is available as SIP core to partners of their Cortex-X Custom (CXC) program, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).^[1][2]

• Samsung Exynos 2100^[8]
• Qualcomm Snapdragon 888(+)^[9]
• Google Tensor^[10]

• ARM Cortex-A78, related high performance microarchitecture
• ARM Neoverse V1 (Zeus), server sister core to the Cortex-X1
• Comparison of ARMv8-A cores, ARMv8 family