The ARM Cortex-A17 is a 32-bit processor core implementing the ARMv7-A architecture, licensed by ARM Holdings. Providing up to four cache-coherent cores, it serves as the successor to the Cortex-A9 and replaces the previous ARM Cortex-A12 specifications.[2] ARM claims that the Cortex-A17 core provides 60% higher performance than the Cortex-A9 core, while reducing the power consumption by 20% under the same workload.[1]
| General information | |
|---|---|
| Designed by | ARM Holdings |
| Performance | |
| Max. CPU clock rate | 1.25 GHz to 2.75 GHz |
| Cache | |
| L1 cache |
|
| L2 cache | 256 KiB–8 MiB[1] (configurable L2 cache controller) |
| Architecture and classification | |
| Instruction set | ARMv7-A |
| Physical specifications | |
| Cores |
|
| History | |
| Predecessor(s) | ARM Cortex-A12 ARM Cortex-A9 |
ARM renamed Cortex-A12 to a variant of Cortex-A17 since the second revision of the A12 core in early 2014, because these two were indistinguishable in performance and all features available in the A17 were used as upgrades in the A12.[3][4]
New features of the Cortex-A17 specification, not found in the Cortex-A9 specification, are all improvements from the third-generation ARM Cortex-A, which also includes the Cortex-A7 and Cortex-A15:[3]
- Hardware virtualization and 40-bit Large Physical Address Extensions (LPAE) addressing
- Full-system coherency, bringing support for the big.LITTLE architecture[1]
- NEON unit, for floating-point data and SIMD processing
- Deeper integer instruction pipeline, with 10–12 stages[5]
- Full out-of-order execution design with load/store units
Modern Linux kernel implementations will report and support the above features thus :
processor : 3model name : ARMv7 Processor rev 1 (v7l)BogoMIPS : 48.00Features : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrmCPU implementer : 0x41CPU architecture: 7CPU variant : 0x0CPU part : 0xc0dCPU revision : 1
